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Preliminary Datasheet
Specifications in this document are tentative and subject to change.
R8C/3JT Group
RENESAS MCU
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
1.
1.1
Overview
Features
The R8C/3JT Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs are designed to maximize EMI/EMS performance. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. The R8C/3JT Group has data flash (1 KB x 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 1 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
1. Overview
1.1.2
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/3JT Group. Table 1.1
Item CPU
Specifications for R8C/3JT Group (1)
Function Central processing unit Specification R8C CPU core * Number of fundamental instructions: 89 * Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 2.7 V to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 1.8 V to 5.5 V) * Multiplier: 16 bits x 16 bits 32 bits * Multiply-accumulate instruction: 16 bits x 16 bits + 32 bits 32 bits * Operation mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.3 Product List for R8C/3JT Group. * Power-on reset * Voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) * Input-only: 1 pin * CMOS I/O ports: 31, selectable pull-up resistor * High current drive ports: 31 * 3 circuits: XIN clock oscillation circuit, High-speed on-chip oscillator (with frequency adjustment function), Low-speed on-chip oscillator * Oscillation stop detection: XIN clock oscillation stop detection function * Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 * Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode * Number of interrupt vectors: 69 * External Interrupt: 8 (INT x 4, Key input x 4) * Priority levels: 7 levels * 14 bits x 1 (with prescaler) * Reset start selectable * Low-speed on-chip oscillator for watchdog timer selectable * 1 channel * Activation sources: 22 * Transfer modes: 2 (normal mode, repeat mode) 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits x 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin)
ROM, RAM, Data flash Power Supply Voltage detection Voltage circuit Detection I/O Ports Programmable I/O ports Clock Clock generation circuits
Memory
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
Timer RA
Timer RB
Timer RC
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
1. Overview
Table 1.2
Item Serial Interface LIN Module A/D Converter
Specifications for R8C/3JT Group (2)
Function UART0 UART2 Specification Clock synchronous serial I/O/UART Clock synchronous serial I/O/UART, I2C mode (I2C-bus), SSU mode, multiprocessor communication function Hardware LIN: 1 (timer RA, UART0) 10-bit resolution x 12 channels, includes sample and hold function, with sweep mode System CH x 3, electrostatic capacitive touch detection x 22 * Programming and erasure voltage: VCC = 2.7 V to 5.5 V * Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM) * Program security: ROM code protect, ID code check * Debug functions: On-chip debug, on-board flash rewrite function * Background operation (BGO) function f(XIN) = 20 MHz (VCC = 2.7 V to 5.5 V) f(XIN) = 5 MHz (VCC = 1.8 V to 5.5 V) Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 3.5 A (VCC = 3.0 V, wait mode) Typ. 2.0 A (VCC = 3.0 V, stop mode) -20 to 85C (N version) -40 to 85C (D version) (1) 40-pin HXQFN Package code: PXQN0040LA-A
Sensor Control Unit Flash Memory
Operating Frequency/Supply Voltage Current Consumption
Operating Ambient Temperature Package
Note: 1. Specify the D version if D version functions are to be used.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 3 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
1. Overview
1.2
Product List
Table 1.3 lists Product List for R8C/3JT Group. Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/3JT Group. Table 1.3 Product List for R8C/3JT Group ROM Capacity Program ROM Data flash 16 Kbytes 1 Kbyte x 4 24 Kbytes 1 Kbyte x 4 32 Kbytes 1 Kbyte x 4 16 Kbytes 1 Kbyte x 4 24 Kbytes 1 Kbyte x 4 32 Kbytes 1 Kbyte x 4 RAM Capacity 1.5 Kbytes 2 Kbytes 2.5 Kbytes 1.5 Kbytes 2 Kbytes 2.5 Kbytes Current of Jul 2010 Package Type Remarks
Part No. R5F213J4TNNP (D) R5F213J5TNNP (D) R5F213J6TNNP (D) R5F213J4TDNP (D) R5F213J5TDNP (D) R5F213J6TDNP (D) (D): Under development
PXQN0040LA-A N version PXQN0040LA-A PXQN0040LA-A PXQN0040LA-A D version PXQN0040LA-A PXQN0040LA-A
Part No. R 5 F 21 3J 6 T N XXX NP
Package type: NP: PXQN0040LA-A (0.4 mm pin-pitch, 5 mm square body) ROM number Classification N: Operating ambient temperature -20C to 85C D: Operating ambient temperature -40C to 85C ROM capacity 4: 16 KB 5: 24 KB 6: 32 KB R8C/3JT Group R8C/3x Series Memory type F: Flash memory Renesas MCU Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/3JT Group
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 4 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
1. Overview
1.3
Block Diagram
Figure 1.2 shows a Block Diagram.
8
8
7
5
3
1
I/O ports Peripheral functions
Timers Timer RA (8 bits x 1) Timer RB (8 bits x 1) Timer RC (16 bits x 1)
Port P0
Port P1
Port P2
Port P3
Port P4
UART or clock synchronous serial I/O (8 bits x 2) LIN module
System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator
Sensor Control Unit Watchdog timer (14 bits) Low-speed on-chip oscillator for watchdog timer
A/D converter (10 bits x 12 channels)
Voltage detection circuit
DTC
R8C CPU core
R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG
Memory
ROM (1)
RAM (2)
Multiplier
Notes: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type.
Figure 1.2
Block Diagram
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
1. Overview
1.4
Pin Assignment
Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number.
30 29 28 27 26 25 24 23 22 21
NC P0_7/CH4/AN0(/TRCIOC) P0_6/CH3/AN1(/TRCIOD) P0_5/CH2/AN2(/TRCIOB) P0_4/CH1/AN3(/TRCIOB) P0_3/CH0/AN4(/TRCIOB) P0_2/CHxA/AN5(/TRCIOA/TRCTRG) P0_1/CHxB/AN6(/TRCIOA/TRCTRG) P0_0/CHxC/AN7(/TRCIOA/TRCTRG) NC
P3_1/CH14/TRBO(/TRCIOA/TRCTRG/CTS2/RTS2)
P1_1/CH6/AN9/KI1(/TRCIOA/TRCTRG)
P4_5/CH13/ADTRG/INT0(/RXD2/SCL2)
P1_3/CH8/AN11/Kl3/TRBO(/TRCIOC)
P1_5/CH10(/INT1/RXD0/TRAIO)
P1_2/CH7/AN10/Kl2(/TRCIOB)
P1_0/CH5/AN8/KI0(/TRCIOD)
P1_4/CH9(/TXD0/TRCCLK)
P1_7/CH12/INT1(/TRAIO)
P1_6/CH11(/CLK0)
31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10
20 19 18
NC P2_0/CH15(/INT1/TRCIOB/RXD2/SCL2/TXD2/SDA2) P2_1/CH16(/TRCIOC/CLK2) P2_2/CH17(/TRCIOD/RXD2/SCL2/TXD2/SDA2) P2_3/CH18 P2_4/CH19 P2_5/CH20 P2_6/CH21 P3_3/SCUTRG/INT3/TRBO(/CTS2/RTS2/TRCCLK) P3_4/INT2(/RXD2/SCL2/TXD2/SDA2/TRCIOC)
R8C/3JT Group
PXQN0040LA-A (top view)
17 16 15 14 13 12 11
P4_2/VREF
P3_7/TRAO(/RXD2/SCL2/TXD2/SDA2/TRCCLK/INT3)
MODE
VSS/AVSS
RESET
P3_5/TRAIO(/CLK2/TRCIOD/INT1)
P4_6/XIN
P4_7/XOUT
Notes: 1. Can be assigned to the pin in parentheses by a program. NC: Non-Connection 2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3
Pin Assignment (Top View)
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
VCC/AVCC
NC
Page 6 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
1. Overview
Table 1.4
Pin Number 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 21
Pin Name Information by Pin Number
Control Pin Port P4_2 MODE RESET XOUT VSS/AVSS XIN VCC/AVCC P4_7 P4_6 P3_7 P3_5 P3_4 P3_3 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P3_1 (INT3) (INT1) INT2 INT3 TRAO/ (TRCCLK) TRAIO/ (TRCIOD) (TRCIOC) TRBO/ (TRCCLK) (RXD2/SCL2/ TXD2/SDA2) (CLK2) (RXD2/SCL2/ TXD2/SDA2) (CTS2/RTS2) SCUTRG CH21 CH20 CH19 CH18 CH17 CH16 CH15 CH14 Interrupt I/O Pin Functions for Peripheral Modules Timer Serial Interface A/D Converter Sensor Control Unit VREF
(TRCIOD) (TRCIOC) (TRCIOB) TRBO/ (TRCTRG/ TRCIOA) INT0 INT1 (INT1) KI3 KI2 KI1 KI0 (TRAIO) (TRAIO) (TRCCLK) TRBO (/TRCIOC) (TRCIOB) (TRCIOA/ TRCTRG) (TRCIOD) (TRCIOC) (TRCIOD) (TRCIOB) (TRCIOB) (TRCIOB) (TRCIOA/ TRCTRG) (TRCIOA/ TRCTRG) (TRCIOA/ TRCTRG)
(INT1)
(RXD2/TXD2/ SCL2/SDA2) (CLK2) (RXD2/TXD2/ SCL2/SDA2) (CTS2/RTS2)
22 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 39
P4_5 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0
(RXD2/SCL2) (CLK0) (RXD0) (TXD0)
ADTRG
CH13 CH12 CH11 CH10
AN11 AN10 AN9 AN8 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 CHxA CHxB CHxC
Note: 1. Can be assigned to the pin in parentheses by a program.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
1. Overview
1.5
Pin Functions
Table 1.5 lists Pin Functions. Table 1.5
Item Power supply input Analog power supply input Reset input MODE XIN clock input XIN clock output
Pin Functions
Pin Name VCC, VSS AVCC, AVSS RESET MODE XIN XOUT I/O Type -- -- I I I I/O I I I/O O O I I I/O I/O I O I O I/O I/O I I I I/O I I I/O Description Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Input "L" on this pin resets the MCU. Connect this pin to VCC via a resistor. These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. (1) To use an external clock, input it to the XOUT pin and leave the XIN pin open. INT interrupt input pins. INT0 is timer RB, and RC input pin. Key input interrupt input pins Timer RA I/O pin Timer RA output pin Timer RB output pin External clock input pin External trigger input pin Timer RC I/O pins Transfer clock I/O pins Serial data input pins Serial data output pins Transmission control input pin Reception control output pin I2C mode clock I/O pin I2C mode data I/O pin Reference voltage input pin to A/D converter Analog input pins to A/D converter AD external trigger input pin Control pins for electrostatic capacitive touch detection Electrostatic capacitive touch detection pins Sensor control unit external trigger input CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. All ports can be used as LED drive ports. Input-only port
INT interrupt input Key input interrupt Timer RA Timer RB Timer RC
INT0 to INT3 KI0 to KI3 TRAIO TRAO TRBO TRCCLK TRCTRG TRCIOA, TRCIOB, TRCIOC, TRCIOD CLK0, CLK2 RXD0, RXD2 TXD0, TXD2 CTS2 RTS2 SCL2 SDA2
Serial interface
Reference voltage input A/D converter Sensor control unit
VREF AN0 to AN11 ADTRG CHxA, CHxB, CHxC CH0 to CH21 SCUTRG P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_6, P3_1, P3_3 to P3_5, P3_7, P4_5 to P4_7 P4_2
I/O port
Input port
I
I: Input O: Output I/O: Input and output Note: 1. Refer to the oscillator manufacturer for oscillation characteristics.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank.
b31
b15
b8b7
b0
R2 R3
R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers (1)
R2 R3 A0 A1 FB
b19 b15 b0
Address registers (1) Frame base register (1)
INTBH
INTBL
Interrupt table register
The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL.
b19 b0
PC
Program counter
b15
b0
USP ISP SB
b15 b0
User stack pointer Interrupt stack pointer Static base register
FLG
b15 b8 b7 b0
Flag register
IPL
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit
Note: 1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
2. Central Processing Unit (CPU)
2.1
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
2. Central Processing Unit (CPU)
2.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
3. Memory
3.
3.1
Memory
R8C/3JT Group
Figure 3.1 is a Memory Map of R8C/3JT Group. The R8C/3JT Group has a 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt routine is stored here. The internal ROM (data flash) is allocated addresses 03000h to 03FFFh. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be accessed by users.
00000h
SFR (Refer to 4. Special Function Registers (SFRs))
002FFh 00400h
Internal RAM
0XXXXh
0FFD8h
Reserved area
SFR (Refer to 4. Special Function Registers (SFRs))
02C00h 02FFFh 03000h
0FFDCh
Internal ROM (data flash) (1)
03FFFh 0YYYYh
Undefined instruction Overflow BRK instruction Address match Single step
Watchdog timer, oscillation stop detection, voltage monitor
Internal ROM (program ROM)
0FFFFh
0FFFFh
Address break (Reserved) Reset
Internal ROM (program ROM)
ZZZZZh FFFFFh
Notes: 1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte). 2. The blank areas are reserved and cannot be accessed by users. Internal ROM Size 16 Kbytes 24 Kbytes 32 Kbytes Address 0YYYYh 0C000h 0A000h 08000h Address ZZZZZh - - - Size 1.5 Kbytes 2 Kbytes 2.5 Kbytes Internal RAM Address 0XXXXh 009FFh 00BFFh 00DFFh
Part Number R5F213J4TNNP, R5F213J4TDNP R5F213J5TNNP, R5F213J5TDNP R5F213J6TNNP, R5F213J6TDNP
Figure 3.1
Memory Map of R8C/3JT Group
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special function registers. Table 4.13 lists the ID Code Areas and Option Function Select Area. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h
SFR Information (1) (1)
Register Symbol After Reset
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Module Standby Control Register System Clock Control Register 3 Protect Register Reset Source Determination Register Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register
PM0 PM1 CM0 CM1 MSTCR CM3 PRCR RSTFR OCD WDTR WDTS WDTC
00h 00h 00101000b 00100000b 00h 00h 00h 0XXXXXXXb (2) 00000100b XXh XXh 00111111b
High-Speed On-Chip Oscillator Control Register 7
FRA7
When shipping
Count Source Protection Mode Register
CSPR
00h 10000000b (3)
High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 On-Chip Reference Voltage Control Register Clock Prescaler Reset Flag High-Speed On-Chip Oscillator Control Register 4 High-Speed On-Chip Oscillator Control Register 5 High-Speed On-Chip Oscillator Control Register 6
FRA0 FRA1 FRA2 OCVREFCR CPSRF FRA4 FRA5 FRA6
00h When shipping 00h 00h 00h When shipping When shipping When shipping
High-Speed On-Chip Oscillator Control Register 3 Voltage Monitor Circuit Control Register Voltage Monitor Circuit Edge Select Register Voltage Detect Register 1 Voltage Detect Register 2
FRA3 CMPA VCAC VCA1 VCA2
When shipping 00h 00h 00001000b 00h (4) 00100000b (5) 00000111b 1100X010b (4) 1100X011b (5) 10001010b
Voltage Detection 1 Level Select Register Voltage Monitor 0 Circuit Control Register
VD1LS VW0C
0039h Voltage Monitor 1 Circuit Control Register VW1C X: Undefined Notes: 1. The blank areas are reserved and cannot be accessed by users. 2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, Software reset, or watchdog timer reset does not affect this bit. 3. The CSPROINI bit in the OFS register is set to 0. 4. The LVDAS bit in the OFS register is set to 1. 5. The LVDAS bit in the OFS register is set to 0.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.2
SFR Information (2) (1)
Symbol VW2C After Reset 10000010b
Address Register 003Ah Voltage Monitor 2 Circuit Control Register 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h Flash Memory Ready Interrupt Control Register 0042h 0043h 0044h 0045h 0046h 0047h Timer RC Interrupt Control Register 0048h 0049h 004Ah 004Bh UART2 Transmit Interrupt Control Register 004Ch UART2 Receive Interrupt Control Register 004Dh Key Input Interrupt Control Register 004Eh A/D Conversion Interrupt Control Register 004Fh 0050h 0051h UART0 Transmit Interrupt Control Register 0052h UART0 Receive Interrupt Control Register 0053h 0054h 0055h INT2 Interrupt Control Register 0056h Timer RA Interrupt Control Register 0057h 0058h Timer RB Interrupt Control Register 0059h INT1 Interrupt Control Register 005Ah INT3 Interrupt Control Register 005Bh 005Ch 005Dh INT0 Interrupt Control Register 005Eh UART2 Bus Collision Detection Interrupt Control Register 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah Sensor Control Unit Interrupt Control Register 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h Voltage Monitor 1 Interrupt Control Register 0073h Voltage Monitor 2 Interrupt Control Register 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
FMRDYIC
XXXXX000b
TRCIC
XXXXX000b
S2TIC S2RIC KUPIC ADIC
XXXXX000b XXXXX000b XXXXX000b XXXXX000b
S0TIC S0RIC
XXXXX000b XXXXX000b
INT2IC TRAIC TRBIC INT1IC INT3IC
XX00X000b XXXXX000b XXXXX000b XX00X000b XX00X000b
INT0IC U2BCNIC
XX00X000b XXXXX000b
SCUIC
XXXXX000b
VCMP1IC VCMP2IC
XXXXX000b XXXXX000b
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 14 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.3
SFR Information (3) (1)
Symbol DTCTL After Reset 00h
Address Register 0080h DTC Activation Control Register 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h DTC Activation Enable Register 0 0089h DTC Activation Enable Register 1 008Ah DTC Activation Enable Register 2 008Bh DTC Activation Enable Register 3 008Ch 008Dh DTC Activation Enable Register 5 008Eh DTC Activation Enable Register 6 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h UART0 Transmit/Receive Mode Register 00A1h UART0 Bit Rate Register 00A2h UART0 Transmit Buffer Register 00A3h 00A4h UART0 Transmit/Receive Control Register 0 00A5h UART0 Transmit/Receive Control Register 1 00A6h UART0 Receive Buffer Register 00A7h 00A8h UART2 Transmit/Receive Mode Register 00A9h UART2 Bit Rate Register 00AAh UART2 Transmit Buffer Register 00ABh 00ACh UART2 Transmit/Receive Control Register 0 00ADh UART2 Transmit/Receive Control Register 1 00AEh UART2 Receive Buffer Register 00AFh 00B0h UART2 Digital Filter Function Select Register 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh UART2 Special Mode Register 5 00BCh UART2 Special Mode Register 4 00BDh UART2 Special Mode Register 3 00BEh UART2 Special Mode Register 2 00BFh UART2 Special Mode Register X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
DTCEN0 DTCEN1 DTCEN2 DTCEN3 DTCEN5 DTCEN6
00h 00h 00h 00h 00h 00h
U0MR U0BRG U0TB U0C0 U0C1 U0RB U2MR U2BRG U2TB U2C0 U2C1 U2RB URXDF
00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h
U2SMR5 U2SMR4 U2SMR3 U2SMR2 U2SMR
00h 00h 000X0X0Xb X0000000b X0000000b
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 15 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.4
SFR Information (4) (1)
Symbol AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 After Reset XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb XXh 000000XXb
Address Register 00C0h A/D Register 0 00C1h 00C2h A/D Register 1 00C3h 00C4h A/D Register 2 00C5h 00C6h A/D Register 3 00C7h 00C8h A/D Register 4 00C9h 00CAh A/D Register 5 00CBh 00CCh A/D Register 6 00CDh 00CEh A/D Register 7 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h A/D Mode Register 00D5h A/D Input Select Register 00D6h A/D Control Register 0 00D7h A/D Control Register 1 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h Port P0 Register 00E1h Port P1 Register 00E2h Port P0 Direction Register 00E3h Port P1 Direction Register 00E4h Port P2 Register 00E5h Port P3 Register 00E6h Port P2 Direction Register 00E7h Port P3 Direction Register 00E8h Port P4 Register 00E9h 00EAh Port P4 Direction Register 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
ADMOD ADINSEL ADCON0 ADCON1
00h 11000000b 00h 00h
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 PD4
XXh XXh 00h 00h XXh XXh 00h 00h XXh 00h
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 16 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.5
SFR Information (5) (1)
Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR2 LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR After Reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh
Address Register 0100h Timer RA Control Register 0101h Timer RA I/O Control Register 0102h Timer RA Mode Register 0103h Timer RA Prescaler Register 0104h Timer RA Register 0105h LIN Control Register 2 0106h LIN Control Register 0107h LIN Status Register 0108h Timer RB Control Register 0109h Timer RB One-Shot Control Register 010Ah Timer RB I/O Control Register 010Bh Timer RB Mode Register 010Ch Timer RB Prescaler Register 010Dh Timer RB Secondary Register 010Eh Timer RB Primary Register 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h Timer RC Mode Register 0121h Timer RC Control Register 1 0122h Timer RC Interrupt Enable Register 0123h Timer RC Status Register 0124h Timer RC I/O Control Register 0 0125h Timer RC I/O Control Register 1 0126h Timer RC Counter 0127h 0128h Timer RC General Register A 0129h 012Ah Timer RC General Register B 012Bh 012Ch Timer RC General Register C 012Dh 012Eh Timer RC General Register D 012Fh 0130h Timer RC Control Register 2 0131h Timer RC Digital Filter Function Select Register 0132h Timer RC Output Master Enable Register 0133h Timer RC Trigger Control Register 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh Note: 1. The blank areas are reserved and cannot be accessed by users.
TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC TRCGRA TRCGRB TRCGRC TRCGRD TRCCR2 TRCDF TRCOER TRCADCR
01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011000b 00h 01111111b 00h
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 17 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.6
SFR Information (6) (1)
Symbol After Reset
Address Register 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh Note: 1. The blank areas are reserved and cannot be accessed by users.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 18 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.7
SFR Information (7) (1)
Symbol TRASR TRBRCSR TRCPSR0 TRCPSR1 After Reset 00h 00h 00h 00h
Address Register 0180h Timer RA Pin Select Register 0181h Timer RB/RC Pin Select Register 0182h Timer RC Pin Select Register 0 0183h Timer RC Pin Select Register 1 0184h 0185h 0186h 0187h 0188h UART0 Pin Select Register 0189h 018Ah UART2 Pin Select Register 0 018Bh UART2 Pin Select Register 1 018Ch 018Dh 018Eh INT Interrupt Input Pin Select Register 018Fh I/O Function Pin Select Register 0190h Low-Voltage Signal Mode Control Register 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h Flash Memory Status Register 01B3h 01B4h Flash Memory Control Register 0 01B5h Flash Memory Control Register 1 01B6h Flash Memory Control Register 2 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
U0SR U2SR0 U2SR1
00h 00h 00h
INTSR PINSR TSMR
00h 00h 00h
FST FMR0 FMR1 FMR2
10000X00b 00h 00h 00h
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 19 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.8
SFR Information (8) (1)
Symbol RMAD0 After Reset XXh XXh 0000XXXXb 00h XXh XXh 0000XXXXb 00h
Address Register 01C0h Address Match Interrupt Register 0 01C1h 01C2h 01C3h Address Match Interrupt Enable Register 0 01C4h Address Match Interrupt Register 1 01C5h 01C6h 01C7h Address Match Interrupt Enable Register 1 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h Pull-Up Control Register 0 01E1h Pull-Up Control Register 1 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h Port P1 Drive Capacity Control Register 01F1h Port P2 Drive Capacity Control Register 01F2h Drive Capacity Control Register 0 01F3h Drive Capacity Control Register 1 01F4h 01F5h Input Threshold Control Register 0 01F6h Input Threshold Control Register 1 01F7h 01F8h 01F9h 01FAh External Input Enable Register 0 01FBh 01FCh INT Input Filter Select Register 0 01FDh 01FEh Key Input Enable Register 0 01FFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
AIER0 RMAD1
AIER1
PUR0 PUR1
00h 00h
P1DRR P2DRR DRR0 DRR1 VLT0 VLT1
00h 00h 00h 00h 00h 00h
INTEN INTF KIEN
00h 00h 00h
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 20 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.9
SFR Information (9) (1)
Symbol SCUCR0 SCUMR SCTCR0 SCTCR1 SCTCR2 SCTCR3 SCHCR SCUCHC SCUFR SCUSTC SCSCSR SCUSCC After Reset 00h 00h 00000011b 00000001b 00010000b 00h 00h 00h 00h 00h 00000111b 00000111b
Address Register 02C0h SCU Control Register 0 02C1h SCU Mode Register 02C2h SCU Timing Control Register 0 02C3h SCU Timing Control Register 1 02C4h SCU Timing Control Register 2 02C5h SCU Timing Control Register 3 02C6h SCU Channel Control Register 02C7h SCU Channel Control Counter 02C8h SCU Flag Register 02C9h SCU Status Counter 02CAh SCU Secondary Counter Set Register 02CBh SCU Secondary Counter 02CCh 02CDh 02CEh SCU Destination Address Register 02CFh 02D0h SCU Data Buffer Register 02D1h 02D2h SCU Primary Counter 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh Touch Sensor Input Enable Register 0 02DDh Touch Sensor Input Enable Register 1 02DEh Touch Sensor Input Enable Register 2 02DFh : 2C00h DTC Transfer Vector Area 2C01h DTC Transfer Vector Area 2C02h DTC Transfer Vector Area 2C03h DTC Transfer Vector Area 2C04h DTC Transfer Vector Area 2C05h DTC Transfer Vector Area 2C06h DTC Transfer Vector Area 2C07h DTC Transfer Vector Area 2C08h DTC Transfer Vector Area 2C09h DTC Transfer Vector Area 2C0Ah DTC Transfer Vector Area : DTC Transfer Vector Area : DTC Transfer Vector Area 2C3Ah DTC Transfer Vector Area 2C3Bh DTC Transfer Vector Area 2C3Ch DTC Transfer Vector Area 2C3Dh DTC Transfer Vector Area 2C3Eh DTC Transfer Vector Area 2C3Fh DTC Transfer Vector Area 2C40h DTC Control Data 0 2C41h 2C42h 2C43h 2C44h 2C45h 2C46h 2C47h 2C48h DTC Control Data 1 2C49h 2C4Ah 2C4Bh 2C4Ch 2C4Dh 2C4Eh 2C4Fh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
SCUDAR SCUDBR SCUPRC
00h 00001100b 00h 00h 00h 00h
TSIER0 TSIER1 TSIER2
00h 00h 00h
DTCD0
DTCD1
XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 21 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.10
SFR Information (10) (1)
Symbol DTCD2 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
Address Register 2C50h DTC Control Data 2 2C51h 2C52h 2C53h 2C54h 2C55h 2C56h 2C57h 2C58h DTC Control Data 3 2C59h 2C5Ah 2C5Bh 2C5Ch 2C5Dh 2C5Eh 2C5Fh 2C60h DTC Control Data 4 2C61h 2C62h 2C63h 2C64h 2C65h 2C66h 2C67h 2C68h DTC Control Data 5 2C69h 2C6Ah 2C6Bh 2C6Ch 2C6Dh 2C6Eh 2C6Fh 2C70h DTC Control Data 6 2C71h 2C72h 2C73h 2C74h 2C75h 2C76h 2C77h 2C78h DTC Control Data 7 2C79h 2C7Ah 2C7Bh 2C7Ch 2C7Dh 2C7Eh 2C7Fh 2C80h DTC Control Data 8 2C81h 2C82h 2C83h 2C84h 2C85h 2C86h 2C87h 2C88h DTC Control Data 9 2C89h 2C8Ah 2C8Bh 2C8Ch 2C8Dh 2C8Eh 2C8Fh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
DTCD3
DTCD4
DTCD5
DTCD6
DTCD7
DTCD8
DTCD9
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 22 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.11
SFR Information (11) (1)
Symbol DTCD10 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
Address Register 2C90h DTC Control Data 10 2C91h 2C92h 2C93h 2C94h 2C95h 2C96h 2C97h 2C98h DTC Control Data 11 2C99h 2C9Ah 2C9Bh 2C9Ch 2C9Dh 2C9Eh 2C9Fh 2CA0h DTC Control Data 12 2CA1h 2CA2h 2CA3h 2CA4h 2CA5h 2CA6h 2CA7h 2CA8h DTC Control Data 13 2CA9h 2CAAh 2CABh 2CACh 2CADh 2CAEh 2CAFh 2CB0h DTC Control Data 14 2CB1h 2CB2h 2CB3h 2CB4h 2CB5h 2CB6h 2CB7h 2CB8h DTC Control Data 15 2CB9h 2CBAh 2CBBh 2CBCh 2CBDh 2CBEh 2CBFh 2CC0h DTC Control Data 16 2CC1h 2CC2h 2CC3h 2CC4h 2CC5h 2CC6h 2CC7h 2CC8h DTC Control Data 17 2CC9h 2CCAh 2CCBh 2CCCh 2CCDh 2CCEh 2CCFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
DTCD11
DTCD12
DTCD13
DTCD14
DTCD15
DTCD16
DTCD17
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 23 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.12
SFR Information (12) (1)
Symbol DTCD18 After Reset XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
Address Register 2CD0h DTC Control Data 18 2CD1h 2CD2h 2CD3h 2CD4h 2CD5h 2CD6h 2CD7h 2CD8h DTC Control Data 19 2CD9h 2CDAh 2CDBh 2CDCh 2CDDh 2CDEh 2CDFh 2CE0h DTC Control Data 20 2CE1h 2CE2h 2CE3h 2CE4h 2CE5h 2CE6h 2CE7h 2CE8h DTC Control Data 21 2CE9h 2CEAh 2CEBh 2CECh 2CEDh 2CEEh 2CEFh 2CF0h DTC Control Data 22 2CF1h 2CF2h 2CF3h 2CF4h 2CF5h 2CF6h 2CF7h 2CF8h DTC Control Data 23 2CF9h 2CFAh 2CFBh 2CFCh 2CFDh 2CFEh 2CFFh 2D00h : 2FFFh X: Undefined Note: 1. The blank areas are reserved and cannot be accessed by users.
DTCD19
DTCD20
DTCD21
DTCD22
DTCD23
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 24 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
4. Special Function Registers (SFRs)
Table 4.13
ID Code Areas and Option Function Select Area
Address Area Name Symbol After Reset : FFDBh Option Function Select Register 2 OFS2 (Note 1) : FFDFh ID1 (Note 2) : FFE3h ID2 (Note 2) : FFEBh ID3 (Note 2) : FFEFh ID4 (Note 2) : FFF3h ID5 (Note 2) : FFF7h ID6 (Note 2) : FFFBh ID7 (Note 2) : FFFFh Option Function Select Register OFS (Note 1) Notes: 1. The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select area is set to FFh. When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user. When factory-programming products are shipped, the value of the option function select area is the value programmed by the user. 2. The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program. Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh. When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user. When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 25 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
5.
Electrical Characteristics
Table 5.1
Symbol VCC/AVCC VI VO Pd Topr Tstg
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Output voltage Power dissipation Operating ambient temperature Storage temperature -40C Topr 85C Condition Rated Value -0.3 to 6.5 -0.3 to Vcc + 0.3 -0.3 to Vcc + 0.3 500 -20 to 85 (N version)/ -40 to 85 (D version) -65 to 150 Unit V V V mW C C
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.2
Symbol
Recommended Operating Conditions
Parameter Conditions Standard Min. 1.8 -- Other than CMOS input CMOS Input level Input level selection input switching : 0.35 Vcc function (I/O port) Input level selection : 0.5 Vcc 4.0 V Vcc 5.5 V 2.7 V Vcc < 4.0 V 1.8 V Vcc < 2.7 V 4.0 V Vcc 5.5 V 2.7 V Vcc < 4.0 V 1.8 V Vcc < 2.7 V Input level selection 4.0 V Vcc 5.5 V : 0.7 Vcc 2.7 V Vcc < 4.0 V 1.8 V Vcc < 2.7 V External clock input (XOUT) 0.8 Vcc 0.5 Vcc 0.55 Vcc 0.65 Vcc 0.65 Vcc 0.7 Vcc 0.8 Vcc 0.85 Vcc 0.85 Vcc 0.85 Vcc 1.2 0 4.0 V Vcc 5.5 V 2.7 V Vcc < 4.0 V 1.8 V Vcc < 2.7 V 4.0 V Vcc 5.5 V 2.7 V Vcc < 4.0 V 1.8 V Vcc < 2.7 V Input level selection 4.0 V Vcc 5.5 V : 0.7 Vcc 2.7 V Vcc < 4.0 V 1.8 V Vcc < 2.7 V External clock input (XOUT) 0 0 0 0 0 0 0 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- 2.7 V Vcc 5.5 V 1.8 V Vcc < 2.7 V 2.7 V Vcc 5.5 V 2.7 V Vcc 5.5 V 1.8 V Vcc < 2.7 V 2.7 V Vcc 5.5 V 1.8 V Vcc < 2.7 V 2.7 V Vcc 5.5 V 1.8 V Vcc < 2.7 V -- -- 32 -- -- -- -- -- -- Typ. -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.5 -- Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc 0.2 Vcc 0.2 Vcc 0.2 Vcc 0.2 Vcc 0.4 Vcc 0.3 Vcc 0.2 Vcc 0.55 Vcc 0.45 Vcc 0.35 Vcc 0.4 Vcc -160 -80 -10 -40 -5 -20 160 80 10 40 5 20 20 5 40 20 5 20 5 20 5 Unit V V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz MHz MHz MHz MHz MHz MHz
VCC/AVCC Supply voltage VSS/AVSS Supply voltage VIH Input "H" voltage
VIL
Input "L" voltage
Other than CMOS input CMOS Input level Input level selection input switching : 0.35 Vcc function (I/O port) Input level selection : 0.5 Vcc
IOH(sum) IOH(sum) IOH(peak) IOH(avg) IOL(sum) IOL(sum) IOL(peak) IOL(avg) f(XIN)
Peak sum output "H" current
Sum of all pins IOH(peak)
Average sum Sum of all pins IOH(avg) output "H" current Peak output "H" current Average output "H" current Peak sum output "L" current Average sum output "L" current Peak output "L" current Average output "L" current Drive capacity Low Drive capacity High Drive capacity Low Drive capacity High Sum of all pins IOL(peak) Sum of all pins IOL(avg) Drive capacity Low Drive capacity High Drive capacity Low Drive capacity High
XIN clock input oscillation frequency
fOCO40M When used as the count source for timer RC (3) fOCO-F -- f(BCLK) fOCO-F frequency System clock frequency CPU clock frequency
Notes: 1. Vcc = 1.8 V to 5.5 V at Topr = -20C to 85C (N version)/-40C to 85C (D version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. 3. fOCO40M can be used as the count source for timer RC in the range of Vcc = 2.7 V to 5.5 V.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 27 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
P0 P1 P2 P3 P4
30 pF
Figure 5.1
Ports P0 to P4 Timing Measurement Circuit
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 28 of 47
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Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.3
Symbol -- --
A/D Converter Characteristics
Parameter Resolution Absolute accuracy 10-bit mode Vref = AVcc Vref = AVcc = 5.0 V Vref = AVcc = 3.3 V Vref = AVcc = 3.0 V Vref = AVcc = 2.2 V 8-bit mode Vref = AVcc = 5.0 V Vref = AVcc = 3.3 V Vref = AVcc = 3.0 V Vref = AVcc = 2.2 V AN0 to AN7 input AN8 to AN11 input AN0 to AN7 input AN8 to AN11 input AN0 to AN7 input AN8 to AN11 input AN0 to AN7 input AN8 to AN11 input AN0 to AN7 input AN8 to AN11 input AN0 to AN7 input AN8 to AN11 input AN0 to AN7 input AN8 to AN11 input AN0 to AN7 input AN8 to AN11 input Conditions Standard Min. -- -- -- -- -- -- -- -- -- 2 2 2 2 -- 10-bit mode 8-bit mode Vref = AVcc = 5.0 V, AD = 20 MHz Vref = AVcc = 5.0 V, AD = 20 MHz AD = 20 MHz Vcc = 5.0 V, XIN = f1 = AD = 20 MHz 2.2 2.2 0.75 -- 2.2 0 2 MHz AD 4 MHz 1.19 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- 3 -- -- -- 45 -- -- 1.34 Max. 10 3 5 5 5 2 2 2 2 20 16 10 5 -- -- -- -- -- AVcc Vref 1.49 Unit Bit LSB LSB LSB LSB LSB LSB LSB LSB MHz MHz MHz MHz k s ms s A V V V
AD
A/D conversion clock
4.0 V Vref = AVcc 5.5 V (2) 3.2 V Vref = AVcc 5.5 V (2) 2.7 V Vref = AVcc 5.5 V (2) 2.2 V Vref = AVcc 5.5 V
(2)
-- tCONV tSAMP IVref Vref VIA
Tolerance level impedance Conversion time Sampling time Vref current Reference voltage Analog input voltage (3)
OCVREF On-chip reference voltage
Notes: 1. Vcc/AVcc = Vref = 2.2 V to 5.5 V, Vss = 0 V at Topr = -20C to 85C (N version)/-40C to 85C (D version), unless otherwise specified. 2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-currentconsumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion. 3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode.
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Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.4
Symbol -- -- --
Flash Memory (Program ROM) Electrical Characteristics
Parameter Program/erase endurance (2) Byte program time Block erase time Conditions Standard Min. 1,000 (3) -- -- -- 0 -- -- 2.7 1.8 0 Ambient temperature = 55C 20 Typ. -- 80 0.3 -- -- -- -- -- -- -- -- Max. -- 500 -- 5 + CPU clock x 3 cycles -- 30 + CPU clock x 1 cycle 30 + CPU clock x 1 cycle 5.5 5.5 60 -- Unit times s s ms s s s V V C year
td(SR-SUS) Time delay from suspend request until suspend -- -- Interval from erase start/restart until following suspend request Time from suspend until erase restart
td(CMDRST Time from when command is forcibly -READY) terminated until reading is enabled -- -- -- -- Program, erase voltage Read voltage Program, erase temperature Data hold time (7)
Notes: 1. Vcc = 2.7 V to 5.5 V at Topr = 0C to 60C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.5
Symbol -- -- -- -- --
Flash Memory (Data flash Block A to Block D) Electrical Characteristics
Parameter Program/erase endurance (2) Byte program time (program/erase endurance 1,000 times) Byte program time (program/erase endurance > 1,000 times) Block erase time (program/erase endurance 1,000 times) Block erase time (program/erase endurance > 1,000 times) Conditions Standard Min. 10,000 (3) -- -- -- -- -- 0 -- -- 2.7 1.8 -20 (7) Ambient temperature = 55C 20 Typ. -- 160 300 0.2 0.3 -- -- -- -- -- -- -- -- Max. -- 1,500 1,500 1 1 5 + CPU clock x 3 cycles -- 30 + CPU clock x 1 cycle 30 + CPU clock x 1 cycle 5.5 5.5 85 -- Unit times s s s s ms s s s V V C year
td(SR-SUS) Time delay from suspend request until suspend -- -- Interval from erase start/restart until following suspend request Time from suspend until erase restart
td(CMDRST Time from when command is forcibly -READY) terminated until reading is enabled -- -- -- -- Program, erase voltage Read voltage Program, erase temperature Data hold time (8)
Notes: 1. Vcc = 2.7 V to 5.5 V at Topr = -20C to 85C (N version)/-40C to 85C (D version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. -40C for D version. 8. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request (FMR21 bit) FST7 bit FST6 bit
Fixed time Clock-dependent time Access restart
td(SR-SUS) FST6, FST7: Bit in FST register FMR21: Bit in FMR2 register
Figure 5.2
Time delay until Suspend
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.6
Symbol Vdet0
Voltage Detection 0 Circuit Electrical Characteristics
Parameter Voltage detection level Vdet0_0 (2) Voltage detection level Vdet0_1 (2) Voltage detection level Vdet0_2 (2) Voltage detection level Vdet0_3
(2) (4)
Condition
Standard Min. 1.80 2.15 2.70 3.55 Typ. 1.90 2.35 2.85 3.80 6 1.5 -- Max. 2.05 2.50 3.05 4.05 150 -- 100
Unit V V V V s A s
-- -- td(E-A)
Voltage detection 0 circuit response time
At the falling of Vcc from 5 V to (Vdet0_0 - 0.1) V VCA25 = 1, Vcc = 5.0 V
-- -- --
Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (3)
Notes: 1. The measurement condition is Vcc = 1.8 V to 5.5 V and Topr = -20C to 85C (N version)/-40C to 85C (D version). 2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. 4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.7
Symbol Vdet1
Voltage Detection 1 Circuit Electrical Characteristics
Parameter Voltage detection level Vdet1_0 (2) Voltage detection level Vdet1_1 (2) Voltage detection level Vdet1_2 (2) Voltage detection level Vdet1_3 Voltage detection level Vdet1_4
(2) (2)
Condition At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc At the falling of Vcc Vdet1_0 to Vdet1_5 selected Vdet1_6 to Vdet1_F selected At the falling of Vcc from 5 V to (Vdet1_0 - 0.1) V VCA26 = 1, Vcc = 5.0 V
Standard Min. 2.00 2.15 2.30 2.45 2.60 2.75 2.85 3.00 3.15 3.30 3.45 3.60 3.75 3.90 4.05 4.20 -- -- -- -- -- Typ. 2.20 2.35 2.50 2.65 2.80 2.95 3.10 3.25 3.40 3.55 3.70 3.85 4.00 4.15 4.30 4.45 0.07 0.10 60 1.7 -- Max. 2.40 2.55 2.70 2.85 3.00 3.15 3.40 3.55 3.70 3.85 4.00 4.15 4.30 4.45 4.60 4.75 -- -- 150 -- 100
Unit V V V V V V V V V V V V V V V V V V s A s
Voltage detection level Vdet1_5 (2) Voltage detection level Vdet1_6 (2) Voltage detection level Vdet1_7 Voltage detection level Vdet1_8
(2) (2)
Voltage detection level Vdet1_9 (2) Voltage detection level Vdet1_A (2) Voltage detection level Vdet1_B Voltage detection level Vdet1_C
(2) (2)
Voltage detection level Vdet1_D (2) Voltage detection level Vdet1_E (2) Voltage detection level Vdet1_F (2) -- -- -- td(E-A) Hysteresis width at the rising of Vcc in voltage detection 1 circuit Voltage detection 1 circuit response time
(3)
Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (4)
Notes: 1. The measurement condition is Vcc = 1.8 V to 5.5 V and Topr = -20C to 85C (N version)/-40C to 85C (D version). 2. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register. 3. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 4. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.8
Symbol Vdet2 -- -- -- td(E-A)
Voltage Detection 2 Circuit Electrical Characteristics
Parameter Voltage detection level Vdet2_0 Hysteresis width at the rising of Vcc in voltage detection 2 circuit Voltage detection 2 circuit response time (2) Voltage detection circuit self power consumption Waiting time until voltage detection circuit operation starts (3) At the falling of Vcc from 5 V to (Vdet2_0 - 0.1) V VCA27 = 1, Vcc = 5.0 V Condition At the falling of Vcc Standard Min. 3.70 -- -- -- -- Typ. 4.00 0.10 20 1.7 -- Max. 4.30 -- 150 -- 100 Unit V V s A s
Notes: 1. The measurement condition is Vcc = 1.8 V to 5.5 V and Topr = -20C to 85C (N version)/-40C to 85C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0.
Table 5.9
Symbol trth
Power-on Reset Circuit (2)
Parameter External power Vcc rise gradient (Note 1) Condition Standard Min. 0 Typ. -- Max. Unit
50000 mV/msec
Notes: 1. The measurement condition is Topr = -20C to 85C (N version)/-40C to 85C (D version), unless otherwise specified. 2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Vdet0 (1) trth External Power VCC 0.5 V tw(por) (2) Voltage detection 0 circuit response time trth
Vdet0 (1)
Internal reset signal
1 x 32 fOCO-S
1 x 32 fOCO-S
Notes: 1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit in User's Manual: Hardware for details. 2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain tw(por) for 1 ms or more.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.10
Symbol --
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter Condition Standard Min. TBD TBD TBD TBD TBD TBD -- -- Typ. 40 40 36.864 36.864 32 32 0.5 400 Max. TBD TBD TBD TBD TBD TBD 3 -- Unit MHz MHz MHz MHz MHz MHz ms A
High-speed on-chip oscillator frequency after reset Vcc = 1.8 V to 5.5 V -20C Topr 85C Vcc = 1.8 V to 5.5 V -40C Topr 85C High-speed on-chip oscillator frequency when the FRA4 register correction value is written into the FRA1 register and the FRA5 register correction value into the FRA3 register (2) High-speed on-chip oscillator frequency when the FRA6 register correction value is written into the FRA1 register and the FRA7 register correction value into the FRA3 register Vcc = 1.8 V to 5.5 V -20C Topr 85C Vcc = 1.8 V to 5.5 V -40C Topr 85C Vcc = 1.8 V to 5.5 V -20C Topr 85C Vcc = 1.8 V to 5.5 V -40C Topr 85C Vcc = 5.0 V, Topr = 25C Vcc = 5.0 V, Topr = 25C
-- --
Oscillation stability time Self power consumption at oscillation
Notes: 1. Vcc = 1.8 V to 5.5 V, Topr = -20C to 85C (N version)/-40C to 85C (D version), unless otherwise specified. 2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode.
Table 5.11
Symbol fOCO-S -- --
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Parameter Condition Standard Min. 60 Vcc = 5.0 V, Topr = 25C Vcc = 5.0 V, Topr = 25C -- -- Typ. 125 30 2 Max. 250 100 -- Unit kHz s A
Low-speed on-chip oscillator frequency Oscillation stability time Self power consumption at oscillation
Note: 1. Vcc = 1.8 V to 5.5 V, Topr = -20C to 85C (N version)/-40C to 85C (D version), unless otherwise specified.
Table 5.12
Symbol td(P-R)
Power Supply Circuit Timing Characteristics
Parameter Condition Standard Min. -- Typ. -- Max. 2000 Unit s
Time for internal power supply stabilization during power-on (2)
Notes: 1. The measurement condition is Vcc = 1.8 V to 5.5 V and Topr = 25C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.13
Symbol VOH
Electrical Characteristics (1) [4.2 V Vcc 5.5 V]
Parameter Condition Drive capacity High Vcc = 5 V IOH = -20 mA Drive capacity Low Vcc = 5 V IOH = -5 mA XOUT Vcc = 5 V IOH = -200 A Other than XOUT XOUT Drive capacity High Vcc = 5 V IOL = 20 mA Drive capacity Low Vcc = 5 V IOL = 5 mA Vcc = 5 V IOL = 200 A INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, TRBO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRCTRG, TRCCLK, ADTRG, RXD0, RXD2, CLK0, CLK2, SCL2, SDA2 RESET VI = 5 V, Vcc = 5.0 V VI = 0 V, Vcc = 5.0 V VI = 0 V, Vcc = 5.0 V Standard Min. Vcc - 2.0 Vcc - 2.0 1.0 -- -- -- 0.1 Typ. -- -- -- -- -- -- 1.2 Max. Vcc Vcc Vcc 2.0 2.0 0.5 -- Unit V V V V V V V
Output "H" voltage Output "L" voltage Hysteresis
Other than XOUT
VOL
VT+-VT-
0.1 -- -- 25 -- During stop mode 1.8
1.2 -- -- 50 0.3 --
-- 5.0 -5.0 100 -- --
V A A k M V
IIH IIL RPULLUP RfXIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance XIN
RAM hold voltage
Note: 1. 4.2 V Vcc 5.5 V at Topr = -20C to 85C (N version)/-40C to 85C (D version), f(XIN) = 20 MHz, unless otherwise specified.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.14
Electrical Characteristics (2) [3.3 V Vcc 5.5 V] (Topr = -20C to 85C (N version)/-40C to 85C (D version), unless otherwise specified.)
Parameter Condition
XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed High-speed on-chip oscillator on fOCO-F = 20 MHz on-chip oscillator mode Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-16 MSTTRD = MSTTRC = 1 XIN clock off Low-speed High-speed on-chip oscillator off on-chip oscillator mode Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0
Symbol ICC
Standard Min. -- Typ. 6.5 Max. 15
Unit mA
Power supply current High-speed (Vcc = 3.3 V to 5.5 V) clock mode Single-chip mode, output pins are open, other pins are Vss
--
5.3
12.5
mA
--
3.6
--
mA
--
3
--
mA
--
2.2
--
mA
--
1.5
--
mA
--
7
15
mA
--
3
--
mA
--
1
--
mA
--
90
400
A
Wait mode
XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
--
15
100
A
--
4
90
A
--
3.5
--
A
Stop mode
XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0
--
2
5.0
A
--
5
--
A
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
Timing Requirements (Unless Otherwise Specified: Vcc = 5 V, Vss = 0 V at Topr = 25C) Table 5.15
Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) XOUT input cycle time XOUT input "H" width XOUT input "L" width
5. Electrical Characteristics
External Clock Input (XOUT)
Parameter Standard Min. 50 24 24 Max. -- -- -- Unit ns ns ns
tC(XOUT) tWH(XOUT)
Vcc = 5 V
External clock input
tWL(XOUT)
Figure 5.4
External Clock Input Timing Diagram when Vcc = 5 V
Table 5.16
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. 100 40 40 Max. -- -- -- Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
Vcc = 5 V
TRAIO input
tWL(TRAIO)
Figure 5.5
TRAIO Input Timing Diagram when Vcc = 5 V
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.17
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 200 100 100 -- 0 50 90 Max. -- -- -- 50 -- -- -- Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
Vcc = 5 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0, 2
Figure 5.6
Serial Interface Timing Diagram when Vcc = 5 V
Table 5.18
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input, Key Input Interrupt KIi (i = 0 to 3)
Parameter INTi input "H" width, KIi input "H" width INTi input "L" width, KIi input "L" width Standard Min. 250 (1) 250 (2) Max. -- -- Unit ns ns
Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
Vcc = 5 V
INTi input (i = 0 to 3) KIi input (i = 0 to 3)
tW(INL)
tW(INH)
Figure 5.7
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 5 V
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 38 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.19
Symbol VOH
Electrical Characteristics (3) [2.7 V Vcc < 4.2 V]
Parameter Condition Drive capacity High Drive capacity Low XOUT Other than XOUT XOUT Drive capacity High Drive capacity Low INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, TRBO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRCTRG, TRCCLK, ADTRG, RXD0, RXD2, CLK0, CLK2, SCL2, SDA2 RESET Vcc = 3.0 V IOH = -5 mA IOH = -1 mA IOH = -200 A IOL = 5 mA IOL = 1 mA IOL = 200 A Standard Min. Vcc - 0.5 Vcc - 0.5 1.0 -- -- -- 0.1 Typ. -- -- -- -- -- -- 0.4 Max. Vcc Vcc Vcc 0.5 0.5 0.5 -- Unit V V V V V V V
Output "H" voltage Output "L" voltage Hysteresis
Other than XOUT
VOL
VT+-VT-
Vcc = 3.0 V VI = 3 V, Vcc = 3.0 V VI = 0 V, Vcc = 3.0 V VI = 0 V, Vcc = 3.0 V
0.1 -- -- 42 --
0.5 -- -- 84 0.3 --
-- 4.0
-4.0
V
A A
IIH IIL RPULLUP RfXIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance XIN
168 -- --
k M V
RAM hold voltage
During stop mode
1.8
Note: 1. 2.7 V Vcc < 4.2 V at Topr = -20C to 85C (N version)/-40C to 85C (D version), f(XIN) = 10 MHz, unless otherwise specified.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
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Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.20
Electrical Characteristics (4) [2.7 V Vcc < 3.3 V] (Topr = -20C to 85C (N version)/-40C to 85C (D version), unless otherwise specified.)
Parameter Condition Standard Min. -- Typ. 3.5 Max. 10 Unit mA
Symbol ICC
Power supply current High-speed XIN = 10 MHz (square wave) (Vcc = 2.7 V to 3.3 V) clock mode High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Single-chip mode, No division output pins are open, XIN = 10 MHz (square wave) other pins are Vss
High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8
--
1.5
7.5
mA
High-speed on-chip oscillator mode
XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-16 MSTTRD = MSTTRC = 1
--
7
15
mA
--
3
--
mA
--
4
--
mA
--
1.5
--
mA
--
1
--
mA
Low-speed on-chip oscillator mode Wait mode
XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
--
90
390
A
--
15
90
A
--
4
80
A
--
3.5
--
A
Stop mode
XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0
--
2
5.0
A
--
5
--
A
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 40 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
Timing requirements (Unless Otherwise Specified: Vcc = 3 V, Vss = 0 V at Topr = 25C) Table 5.21
Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) XOUT input cycle time XOUT input "H" width XOUT input "L" width
5. Electrical Characteristics
External Clock Input (XOUT)
Parameter Standard Min. 50 24 24 Max. -- -- -- Unit ns ns ns
tC(XOUT) tWH(XOUT)
Vcc = 3 V
External clock input
tWL(XOUT)
Figure 5.8
External Clock Input Timing Diagram when Vcc = 3 V
Table 5.22
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. 300 120 120 Max. -- -- -- Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
Vcc = 3 V
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when Vcc = 3 V
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 41 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.23
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi Input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 300 150 150 -- 0 70 90 Max. -- -- -- 80 -- -- -- Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
Vcc = 3 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0, 2
Figure 5.10
Serial Interface Timing Diagram when Vcc = 3 V
Table 5.24
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input, Key Input Interrupt KIi (i = 0 to 3)
Parameter INTi input "H" width, KIi input "H" width INTi input "L" width, KIi input "L" width Standard Min. 380 (1) 380 (2) Max. -- -- Unit ns ns
Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
Vcc = 3 V
INTi input (i = 0 to 3) KIi input (i = 0 to 3)
tW(INL)
tW(INH)
Figure 5.11
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 3 V
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 42 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.25
Symbol VOH
Electrical Characteristics (5) [1.8 V Vcc < 2.7 V]
Parameter Condition Drive capacity High Drive capacity Low XOUT Other than XOUT XOUT Drive capacity High Drive capacity Low INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, TRBO, TRCIOA, TRCIOB, TRCIOC, TRCIOD, TRCTRG, TRCCLK, ADTRG, RXD0, RXD2, CLK0, CLK2, SCL2, SDA2 RESET VI = 2.2 V, Vcc = 2.2 V VI = 0 V, Vcc = 2.2 V VI = 0 V, Vcc = 2.2 V IOH = -2 mA IOH = -1 mA IOH = -200 A IOL = 2 mA IOL = 1 mA IOL = 200 A Standard Min. Vcc - 0.5 Vcc - 0.5 1.0 -- -- -- 0.05 Typ. -- -- -- -- -- -- 0.20 Max. Vcc Vcc Vcc 0.5 0.5 0.5 -- Unit V V V V V V V
Output "H" voltage Output "L" voltage Hysteresis
Other than XOUT
VOL
VT+-VT-
0.05 -- -- 70 -- During stop mode 1.8
0.20 -- -- 140 0.3 --
-- 4.0
-4.0
V
A A
IIH IIL RPULLUP RfXIN VRAM
Input "H" current Input "L" current Pull-up resistance Feedback resistance XIN
300 -- --
k M V
RAM hold voltage
Note: 1. 1.8 V Vcc < 2.7 V at Topr = -20C to 85C (N version)/-40C to 85C (D version), f(XIN) = 5 MHz, unless otherwise specified.
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 43 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.26
Electrical Characteristics (6) [1.8 V Vcc < 2.7 V] (Topr = -20C to 85C (N version)/-40C to 85C (D version), unless otherwise specified.)
Parameter Condition Standard Min. -- Typ. 2.2 Max. -- Unit mA
Symbol ICC
Power supply current High-speed XIN = 5 MHz (square wave) (Vcc = 1.8 V to 2.7 V) clock mode High-speed on-chip oscillator off Single-chip mode, Low-speed on-chip oscillator on = 125 kHz output pins are open, No division other pins are Vss XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 High-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator on fOCO-F = 5 MHz Low-speed on-chip oscillator on = 125 kHz No division XIN clock off High-speed on-chip oscillator on fOCO-F = 5 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN clock off High-speed on-chip oscillator on fOCO-F = 4 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-16 MSTTRD = MSTTRC = 1 Low-speed on-chip oscillator mode Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR27 = 1, VCA20 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator off While a WAIT instruction is executed VCA27 = VCA26 = VCA25 = 0, VCA20 = 1 Stop mode XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0
--
0.8
--
mA
--
2.5
10
mA
--
1.7
--
mA
--
1
--
mA
--
90
300
A
--
15
90
A
--
4
80
A
--
3.5
--
A
--
2
5
A
--
5
--
A
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 44 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
Timing requirements (Unless Otherwise Specified: Vcc = 2.2 V, Vss = 0 V at Topr = 25C) Table 5.27
Symbol tc(XOUT) tWH(XOUT) tWL(XOUT) XOUT input cycle time XOUT input "H" width XOUT input "L" width
5. Electrical Characteristics
External Clock Input (XOUT)
Parameter Standard Min. 200 90 90 Max. -- -- -- Unit ns ns ns
tC(XOUT) tWH(XOUT)
Vcc = 2.2 V
External clock input
tWL(XOUT)
Figure 5.12
External Clock Input Timing Diagram when Vcc = 2.2 V
Table 5.28
Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO)
TRAIO Input
Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Standard Min. 500 200 200 Max. -- -- -- Unit ns ns ns
tC(TRAIO) tWH(TRAIO)
Vcc = 2.2 V
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when Vcc = 2.2 V
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 45 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
5. Electrical Characteristics
Table 5.29
Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 2
Serial Interface
Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Standard Min. 800 400 400 -- 0 150 90 Max. -- -- -- 200 -- -- -- Unit ns ns ns ns ns ns ns
tC(CK) tW(CKH)
Vcc = 2.2 V
CLKi
tW(CKL) th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi i = 0, 2
Figure 5.14
Serial Interface Timing Diagram when Vcc = 2.2 V
Table 5.30
Symbol tW(INH) tW(INL)
External Interrupt INTi (i = 0 to 3) Input, Key Input Interrupt KIi (i = 0 to 3)
Parameter INTi input "H" width, KIi input "H" width INTi input "L" width, KIi input "L" width Standard Min. 1000 (1) 1000 (2) Max. -- -- Unit ns ns
Notes: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater.
Vcc = 2.2 V
INTi input (i = 0 to 3) KIi input (i = 0 to 3)
tW(INL)
tW(INH)
Figure 5.15
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 2.2 V
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 46 of 47
Under development
Preliminary document Specifications in this document are tentative and subject to change.
R8C/3JT Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Electronics website.
JEITA Package Code P-HXQFN40-5x5-0.40 RENESAS Code PXQN0040LA-A Previous Code MASS[Typ.] 0.037g
D
30 21
A B
21
3.5
30
31
20
20
31
3.5
E
C0.3
40 11 11 40
Reference Dimension in Millimeters Symbol
1
10
10
1
t
S
e
b
xMSAB
y1 S
S
yS
( Ni/Pd/Au plating )
D E A2 A A1 b b1 e Lp x y y1 t HD HE ZD ZE c c1
Lp
Min Nom Max 4.90 5.00 5.10 4.90 5.00 5.10
0.50 0 0.05 0.15 0.20 0.25 0.40 0.35 0.40 0.45 0.10 0.08 0.10 0.15
A1
C
A
0.125
REJ03B0320-0010 Rev.0.10 Jul 12, 2010
Page 47 of 47
REVISION HISTORY
R8C/3JT Group Datasheet
Description Summary First Edition issued
Rev. 0.10
Date Jul 12, 2010
Page --
All trademarks and registered trademarks are the property of their respective owners. C-1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. 4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. 12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) (Note 2) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries. "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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